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low capacitance, low charge injection, 15 v/+12 v i cmos quad spst switches enhanced product adg1212-ep rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features 1 pf off capacitance 2.6 pf on capacitance <1 pc charge injection 33 v supply range 120 on resistance fully specified at 15 v, +12 v no v l supply required 3 v logic-compatible inputs rail-to-rail operation 16-lead tssop typical power consumption: <0.03 w enhanced product features supports defense and aerospace applications (aqec standard) military temperature range: ?55c to +125c controlled manufacturing baseline one assembly/test site one fabrication site enhanced product change notification qualification data available on request applications automatic test equipment data acquisition systems battery-powered systems sample-and-hold systems audio signal routing video signal routing communication systems functional block diagram adg1212-ep notes 1. switches shown are for logic 1 input. s1 in1 in2 in3 in4 d1 s2 d2 s3 d3 s4 d4 10012-001 figure 1. the ultralow capacitance and charge injection of this switch makes it an ideal solution for data acquisition and sample-and- hold applications, where low glitch and fast settling are required. fast switching speed coupled with high signal bandwidth makes the part suitable for video signal switching. i cmos construction ensures ultralow power dissipation, making the part ideally suited for portable and battery-powered instruments. the adg1212-ep contains four independent single-pole/ single-throw (spst) switches. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. additional application and technical information can be found in the adg1212 data sheet. general description the adg1212-ep is a monolithic complementary metal-oxide semiconductor (cmos) device containing four independently selectable switches designed on an i cmos? (industrial cmos) process. i cmos is a modular manufacturing process combining high voltage cmos and bipolar technologies. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no previous generation of high voltage parts has been able to achieve. unlike analog ics using conventional cmos processes, i cmos components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. product highlights 1. ultralow capacitance. 2. <1 pc charge injection. 3. 3 v logic compatible digital inputs: v ih = 2.0 v, v il = 0.8 v. 4. no v l logic power supply required. 5. ultralow power dissipation: <0.03 w. 6. 16-lead tssop package.
adg1212-ep enhanced product rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 ? enhanced product features ............................................................ 1 ? applications....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? dual supply ................................................................................... 3 ? single supply..................................................................................4 ? absolute maximum ratings ............................................................5 ? esd caution...................................................................................5 ? pin configuration and function descriptions..............................6 ? typical performance characteristics ..............................................7 ? test circuits........................................................................................9 ? outline dimensions ....................................................................... 11 ? ordering guide .......................................................................... 11 ? revision history 11/11revision 0: initial version
enhanced product adg1212-ep rev. 0 | page 3 of 12 specifications dual supply v dd = 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. parameter 25c ?40c to +85c ?55c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance (r on ) 120 typ v s = 10 v, i s = ?1 ma; see figure 15 190 230 260 max v dd = +13.5 v, v ss = ?13.5 v on resistance match between channels (?r on ) 2.5 typ v s = 10 v, i s = ?1 ma 6 10 11 max on resistance flatness (r flat(on) ) 20 typ v s = ?5 v/0 v/+5 v; i s = ?1 ma 57 72 79 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off ) 0.02 na typ v s = 10 v, v d = 10 v; see m figure 11 0.1 0.6 1 na max drain off leakage, i d (off ) 0.02 na typ v s = 10 v, v d = 10 v; see m figure 11 0.1 0.6 1 na max channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 10 v; see figure 12 0.1 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 2.5 pf typ dynamic characteristics 1 t on 65 ns typ r l = 300 , c l = 35 pf 80 95 110 ns max v s = 10 v; see figure 18 t off 80 ns typ r l = 300 , c l = 35 pf 100 115 135 ns max v s = 10 v; see figure 18 charge injection ?0.3 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 19 off isolation 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 13 channel-to-channel crosstalk 90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 14 total harmonic distortion + noise 0.15 % typ r l = 10 k, 5 v rms, f = 20 hz to 20 khz; see figure 17 ?3 db bandwidth 1000 mhz typ r l = 50 , c l = 5 pf; see figure 16 c s (off ) 0.9 pf typ v s = 0 v, f = 1 mhz 1.1 pf max v s = 0 v, f = 1 mhz c d (off ) 1 pf typ v s = 0 v, f = 1 mhz 1.2 pf max v s = 0 v, f = 1 mhz c d , c s (on) 2.6 pf typ v s = 0 v, f = 1 mhz 3 pf max v s = 0 v, f = 1 mhz power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i dd 220 a typ digital inputs = 5 v 420 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i ss 0.001 a typ digital inputs = 5 v 1.0 a max 1 guaranteed by design, not subject to production test.
adg1212-ep enhanced product rev. 0 | page 4 of 12 single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. parameter 25c ?40c to +85c ?55c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 300 typ v s = 0 v to 10 v, i s = ?1 ma; see figure 15 475 567 625 max v dd = 10.8 v, v ss = 0 v on resistance match between channels (r on ) 4.5 typ v s = 0 v to 10 v, i s = ?1 ma 12 26 27 max on resistance flatness (r flat(on) ) 60 typ v s = 3 v/6 v/9 v, i s = ?1 ma leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off ) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 11 0.1 0.6 1 na max drain off leakage, i d (off ) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 11 0.1 0.6 1 na max channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 1 v or 10 v; see figure 12 0.1 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 t on 80 ns typ r l = 300 , c l = 35 pf 105 125 140 ns max v s = 8 v; see figure 18 t off 90 ns typ r l = 300 , c l = 35 pf 115 140 165 ns max v s = 8 v; see figure 18 charge injection 0 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 19 off isolation 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 13 channel-to-channel crosstalk 90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 14 ?3 db bandwidth 900 mhz typ r l = 50 , c l = 5 pf; see figure 16 c s (off ) 1.2 pf typ v s = 6 v, f = 1 mhz 1.4 pf max v s = 6 v, f = 1 mhz c d (off ) 1.3 pf typ v s = 6 v, f = 1 mhz 1.5 pf max v s = 6 v, f = 1 mhz c d , c s (on) 3.2 pf typ v s = 6 v, f = 1 mhz 3.9 pf max v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i dd 220 a typ digital inputs = 5 v 420 a max 1 guaranteed by design, not subject to production test.
enhanced product adg1212-ep rev. 0 | page 5 of 12 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 gnd C 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 100 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current per channel, s or d 25 ma operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 16-lead tssop, ja thermal impedance (4-layer board) 112c/w lead temperature, soldering as per jedec j-std-020 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. table 4. adg1212-ep truth table adg1212-ep inx switch condition 1 on 0 off esd caution
adg1212-ep enhanced product rev. 0 | page 6 of 12 pin configuration and fu nction descriptions top view (not to scale) 1 2 3 4 5 6 7 8 adg1212-ep notes 1. nc = no connect. do not connect to this pin. 16 15 14 13 12 11 10 9 d1 s1 v ss d4 s4 gnd in1 d2 s2 v dd d3 in4 in3 s3 nc in2 10012-002 figure 2. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 in1 logic control input. 2 d1 drain terminal. this pin can be an input or output. 3 s1 source terminal. this pin can be an input or output. 4 v ss most negative power supply potential. 5 gnd ground (0 v) reference. 6 s4 source terminal. this pin can be an input or output. 7 d4 drain terminal. this pin can be an input or output. 8 in4 logic control input. 9 in3 logic control input. 10 d3 drain terminal. this pin can be an input or output. 11 s3 source terminal. this pin can be an input or output. 12 nc no connection. 13 v dd most positive power supply potential. 14 s2 source terminal. this pin can be an input or output. 15 d2 drain terminal. this pin can be an input or output. 16 in2 logic control input.
enhanced product adg1212-ep rev. 0 | page 7 of 12 typical performance characteristics v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v source or drain voltage (v) on resistance ( ? ) 200 180 160 140 120 100 60 80 0 20 40 ?18 ?15 ?12 ?9 ?6 ?3 3 9 15 0 6 12 18 10012-003 v dd = +13.5v v ss = ?13.5v t a = +25c figure 3. on resistance as a function of v d (v s ) for dual supply source or drain voltage (v) on resistance ( ? ) 450 400 350 300 250 150 200 0 50 100 ?5 ?4 ?3 ?2 ?1 2 4 01 3 5 10012-004 v dd = +5.5v v ss = ?5.5v t a = +25c figure 4. on resistance as a function of v d (v s ) for dual supply v dd = 13.2v v ss = 0v source or drain voltage (v) on resistance ( ? ) 450 400 350 300 250 150 200 0 50 100 024681012 10012-005 v dd = 12v v ss = 0v v dd = 10.8v v ss = 0v t a = 25c figure 5. on resistance as a function of v d (v s ) for single supply 250 200 150 100 50 0 ?15 ?10 ?5 0 5 10 15 source or drain voltage (v) on resistance ( ? ) 10012-006 v dd = +15v v ss = ?15v t a = +125c t a = +85c t a = +25c t a = ?40c t a = ?55c figure 6. on resistance as a function of v d (v s ) for different temperatures, dual supply 600 500 400 300 200 100 0 02468101 source or drain voltage (v) on resistance ( ? ) 10012-007 2 v dd = 15v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c t a = ?55c figure 7. on resistance as a function of v d (v s ) for different temperatures, single supply temperature (c) leakage (na) 0.20 0.15 0.10 0.05 0 ?0.10 ?0.05 ?0.15 ?0.20 20 04 06 08 0 1 0 0 10012-008 1 2 0 i s (off) i d (off) i d , i s (on) v dd = +15v v ss = ?15v v bias = +10v/?10v figure 8. leakage currents as a function of temperature, dual supply
adg1212-ep enhanced product rev. 0 | page 8 of 12 temperature (c) leakage (na) 0.30 0.25 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 20 04 06 08 0 1 0 0 10012-009 1 2 0 i s (off) i d (off) i d , i s (on) v dd = 12v v ss = 0v v bias = 1v/10v figure 9. leakage currents as a function of temperature, single supply 140 120 100 80 60 40 20 0 ?55 ?35 ?15 4525 5 65 85 105 125 temperature (c) time (ns) 10012-010 t off (12v single supply) t on (12v single supply) t off (15v dual supply) t on (15v dual supply) figure 10. t on /t off times vs. temperature
enhanced product adg1212-ep rev. 0 | page 9 of 12 test circuits sd v s a a v d i s (off) i d (off) 10012-011 figure 11. off leakage i ds v1 sd v s r on = v1/i ds 10012-012 figure 12. on leakage v out 50? network analyzer r l 50 ? in v in s d 50? off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 10012-013 figure 13. off isolation channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50 ? r 50 ? v s v s v dd v ss 0.1f v dd 0.1f v ss 10012-014 figure 14. channel-to-channel crosstalk sd a v d i d (on) nc nc = no connect 10012-015 figure 15. on resistance v out 50? network analyzer r l 50 ? in v in s d insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 10012-016 figure 16. bandwidth v out r s audio precision r l 10k ? in v in s d v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 10012-017 figure 17. thd + noise
adg1212-ep enhanced product rev. 0 | page 10 of 12 v s in sd gnd r l 300 ? c l 35pf v out v dd v ss 0.1f v dd 0.1f v ss adg1212-ep v in v out t on t off 50% 50% 90% 90% 10012-018 figure 18. switching times in v out adg1212-ep v in v out off ? v out on q inj = c l ? v out sd v dd v ss v dd v ss v s r s gnd c l 1nf 10012--019 figure 19. charge injection
enhanced product adg1212-ep rev. 0 | page 11 of 12 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.7 5 0.60 0.4 5 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 20. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model temperature range package description package option ADG1212SRU-EP-RL7 ?55c to +125c 16-lead thin shrink small outline package [tssop] ru-16
adg1212-ep enhanced product rev. 0 | page 12 of 12 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10012-0-11/11(0)

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